1. Field of the Invention
This invention relates to a carrier substrate for mounting of semiconductor chip devices and components where the carrier substrate is resistant to thermal fatigue problems.
2. Discussion of the Background
There is a demand for fast computing devices that require a large amount of power. The large amount of power results in large changes in the temperature of the devices. For example, a part of the device may be at 25° C. when no power is supplied to the device and may reach 100° C. when power is supplied. In addition, these devices can change temperature depending on the level of activity, low and high level of computation in a processor. These extensive and repeated temperature changes cause fatigue of the package and the structure including the package. An electronic package may then fail due to this fatigue. One place where this fatigue occurs is between the layers of a package laminate, or between a packaged part and a PCB (printed circuit board). When one considers building a large area silicon substrate to act as a PCB, it is known by those skilled in the art that the conductors will delaminate or crack due to repeated thermal cycles.
Thus, for fast computing devices that use multiple integrated circuits that are capable of being reprogrammed as necessary during calculations performed by the computing device, the delamination of various layers is present. Standard computing devices include specialized elements that are defined, before being manufactured, to perform one or more functions, as for example dividing or multiplying numbers.
The new computing devices are designed to be reprogrammable, i.e., the functions of the various elements are defined after manufacture, depending of the need of the computing device. These features permit the computing device to reprogram when necessary its elements, resulting in a faster and more compact device. It is estimated that a reprogrammable device achieves a speed from 10 to 100 times faster than a non-programmable device.
However, the new computing devices, by packaging many active elements on a same substrate or multiple substrates stacked together and due to intense computational activity, are producing a large amount of heat that impacts negatively the bonds between the carrier substrate and the conducting layers, which form the power planes and/or the electrical wires. As a result of this repeated thermal stress, the power planes/electrical wires tend to delaminate from the substrate, resulting in a failed structure, as discussed above.
Hichri et al. discloses in U.S. Patent Application Publication No. 2006/0190846, the entire contents of which are incorporated herein by reference, stacked via pillars provided to connect a base substrate to a top oxide cap such that a radial deformation of stacked conductive layers and low-k dielectric material fabricated between the base substrate and the top oxide cap are accommodated during thermal and mechanical stresses.
Edelstein et al. discloses in U.S. Patent Application Publication No. 2006/0027934, the entire contents of which are incorporated herein by reference, a carrier structure provided with through-vias, each through-via having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, to minimize the thermal stress.